1. Field
Example embodiments relate to methods of manufacturing semiconductor devices. More particularly, example embodiments relate to methods of manufacturing a P type metal oxide semiconductor (PMOS) transistor having improved performance and a complementary metal oxide semiconductor (CMOS) transistor having improved performance.
2. Description of the Related Art
A transistor, e.g., a metal oxide semiconductor field effect transistor (MOSFET), may be a basic unit constituting a semiconductor memory device. The transistor operating at a relatively high speed under a relatively low voltage has been developed to have a minute or smaller size and a higher integration degree.
As the semiconductor memory device has been highly integrated, a size of an active region of a substrate also has been scaled down. Thus, a gate length of the transistor formed in the active region may be shorter. When the gate length of the transistor is reduced, a source/drain may exert great influence upon an electric field or an electric potential in a channel region, so that a switching operation by gate voltage may not be properly performed, which may be called a “short-channel effect”. That is, as the gate length has become shortened, the channel region may be influenced by the electric charge, electric field and potential distribution in a depletion layer of a source/drain region in addition to the gate voltage, so that the normal switching operation may be difficult.
In addition, as drain voltage increases, the size of drain depletion layer may also increase, so that the drain depletion layer may approach a source. When the gate length is shortened, the drain depletion layer may be integrally connected to a source depletion layer. In this case, a drain electric filed may exert an influence upon the source, thereby lowering diffusion potential around the source. Thus, current may flow between the source and the drain even if a channel is not formed therebetween, otherwise know as a “punch through phenomenon”. If the punch through phenomenon occurs, the drain current may not be saturated, but may increase even in a saturation area.
Such a short channel effect may become severe as a junction depth of the source/drain region increases or a channel doping lowers. In order to reduce the short channel effect, the source/drain may have a shallow junction depth. However, if the source/drain has the shallow junction depth, source/drain resistance may increase.
In addition, a source/drain having a lightly doped drain (LDD) structure has been suggested to prevent or reduce the short channel effect. As semiconductor devices have been highly integrated, various semiconductor manufacturing technologies have been developed. Gate spacers may be formed on both sidewalls of gate electrodes to form an LDD region.
In order to form the source/drain, the source/drain region may be open and source/drain ions may be doped into the source/drain region. A rapid thermal process (RTP) may be performed to activate dopants. When the RTP is performed, impurities may diffuse from the source/drain region in downward, upward, and lateral directions of a substrate. Thus, the interval between the source and the drain may be reduced and impurity concentration in the source/drain region may be lowered, increasing the resistance of the source/drain region. For example, boron (B), which is a P type impurity, may have relatively low diffusion energy, so boron may more easily diffuse onto the substrate, thereby deteriorating the operational characteristics of the transistor.
A gate electrode may include a material having a specific work function to allow the transistor to have a desired threshold voltage. Polysilicon may be used as the gate electrode because the work function of the polysilicon may be properly adjusted according to the conductive type of impurities doped into the polysilicon. In the case of the PMOS transistor, the polysilicon doped with P type impurities, e.g., boron, may be used as the gate electrode. In the case of a N type transistor, the polysilicon doped with N type impurities, e.g., phosphor or arsenic, may be used as the gate electrode. When the polysilicon doped with the impurities is used as the gate electrode, impurity concentration in the gate electrode may be maintained at a predetermined or given level by preventing or reducing impurities from diffusing from the gate electrode. If the impurity concentration in the gate electrode of the PMOS transistor is lowered, a serious gate depletion phenomenon may occur, so that the thickness of a gate oxide layer may be increased, deteriorating the operational characteristics of the transistor.
However, because impurities doped into the source/drain region and the gate electrode continuously diffuse during the thermal processes, reducing the amount of impurity diffusion may be difficult. Because boron used for the PMOS transistor rapidly diffuses as compared with N type impurities, e.g., phosphor or arsenic, the operational characteristics of the PMOS transistor may deteriorate due to the impurity diffusion.